1. Field of the Invention
The present invention relates to an analog-to-digital converter, and more particularly, to multistage pipelined and cyclic analog-to-digital conversion technologies.
2. Description of the Related Art
Recently, cellular phones, which have been provided with various additional functions such as an image capturing function, an image reproducing function, a moving image capturing function, and a moving image reproducing function, increasingly require further reduction in size and power consumption of an analog-to-digital converter (hereinafter referred to as “AD converters”) incorporated therein. One of the forms of such AD converters known to those skilled in the art is a cyclic AD converter having a cyclic configuration (e.g., see Japanese Patent Laid-Open Publication No. Hei 11-145830). FIG. 9 shows the configuration of a conventional cyclic AD converter. In the cyclic AD converter 150 of FIG. 9, an analog signal Vin input through a first switch 152 is sampled by a first amplifier circuit 156 and then converted into a digital value of one bit in an AD conversion circuit 158. The digital value is then converted into an analog value by a DA conversion circuit 160 and subtracted from the input analog signal Vin by a subtractor circuit 162. The output from the subtractor circuit 162 is amplified by a second amplifier circuit 164 for feedback to the first amplifier circuit 156 through a second switch 154. This feedback-based cyclic processing is repeated twelve times to obtain a digital value of 12 bits.
On the other hand, another AD converter is disclosed in Japanese Patent Laid-Open Publication No. Hei 4-26229 (its entirety and FIG. 1), which has two stages including a cyclic conversion portion.
(First Problem)
The cyclic AD converter described in Japanese Patent Laid-Open Publication No. Hei 11-145830 has an advantage over a multistage pipelined AD converter in having a reduced number of constituent elements and thereby a reduced circuit area. However, since the cyclic AD converter may suffer from a reduced conversion speed whereas achieving a reduced circuit area, an efficient configuration has to be implemented for the cyclic AD converter to improve both of these mutually contradictory performances.
(Second Problem)
The cyclic AD conversion portion described in Japanese Patent Laid-Open Publication No. Hei 4-26229 shares the AD conversion circuit, the DA conversion circuit, the subtractor circuit, and the amplifier circuit, thus contributing a reduction in circuit area. However, although the sharing requires higher-speed operations of each circuit, the amplifier circuit, among other things, has a GB (Gain Bandwidth) product limitation, thereby making it difficult to achieve both a high amplification factor and a high-speed operation at the same time. On the other hand, a conventional pipelined configuration of multiple stages is also available as a method which does not require a high-speed operation of individual circuits; however, this configuration results in an increased circuit area. That is, the conventional configuration was particularly difficult to provide both a reduced size and a high-speed operation at the same time. Among other things, the amplifier circuit having a high amplification factor impedes the high-speed operation.